Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump

ABSTRACT

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

RELATED PATENT APPLICATION

This application is a Continuation application of Ser. No. 12/384,977,filed on Apr. 9, 2009, which is a Continuation application of Ser. No.09/837,007, filed on Apr. 18, 2001, now pending, which is aContinuation-in-part of Ser. No. 09/798,654, filed on Mar. 5, 2001, nowU.S. Pat. No. 6,818,545, all of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices,and more particularly, to a method and package for packagingsemiconductor devices.

(2) Description of the Prior Art

Semiconductor device performance improvements are largely achieved byreducing device dimensions, a development that has, at the same time,resulted in considerable increases in device density and devicecomplexity. These developments have resulted in placing increasingdemands on the methods and techniques that are used to access thedevices, also referred to as Input/Output (I/O) capabilities of thedevice. This has led to new methods of packaging semiconductor deviceswhereby structures such as Ball Grid Array (BGA) devices and Column GridArray (CGA) devices have been developed. A Ball Grid Array (BGA) is anarray of solder balls placed on a chip carrier. The balls contact aprinted circuit board in an array configuration where, after reheat, theballs connect the chip to the printed circuit board. BGA's are knownwith 40, 50 and 60 mil spacings. Due to the increased deviceminiaturization, the impact that device interconnects have on deviceperformance and device cost has also become a larger factor in packagedevelopment. Device interconnects, due to their increase in length inorder to package complex devices and connect these devices tosurrounding circuitry, tend to have an increasingly negative impact onthe package performance. For longer and more robust metal interconnects,the parasitic capacitance and resistance of the metal interconnectionincrease, which degrades the chip performance significantly. Ofparticular concern in this respect is the voltage drop along power andground buses and the RC delay that is introduced in the critical signalpaths.

One of the approaches that has been taken to solve these packagingproblems is to develop low resistance metals (such as copper) for theinterconnect wires, while low dielectric constant materials are beingused in between signal lines. Another approach to solve problems of I/Ocapability has been to design chips and chip packaging techniques thatoffer dependable methods of increased interconnecting of chips at areasonable manufacturing cost.

One of the more recent developments that is aimed at increasing theInput-Output (I/O) capabilities of semiconductor device packages is thedevelopment of Flip Chip Packages. Flip-chip technology fabricates bumps(typically Pb/Sn solders) on aluminum pads on a semiconductor device.The bumps are interconnected directly to the package media, which areusually ceramic or plastic based. The flip-chip is bonded face down tothe package medium through the shortest paths. These technologies can beapplied not only to single-chip packaging, but also to higher orintegrated levels of packaging in which the packages are larger, and tomore sophisticated substrates that accommodate several chips to formlarger functional units.

In general, Chip-On-Board (COB) techniques are used to attachsemiconductor dies to a printed circuit board; these techniques includethe technical disciplines of flip chip attachment, wirebonding, and tapeautomated bonding (TAB). Flip chip attachment consists of attaching aflip chip to a printed circuit board or to another substrate. A flipchip is a semiconductor chip that has a pattern or arrays of terminalsthat are spaced around an active surface area of the flip chip, allowingfor face down mounting of the flip chip to a substrate.

Generally, the flip chip active surface has one of the followingelectrical connectors: BGA (wherein an array of minute solder balls iscreated on the surface of the flip chip that attaches to the substrate);Slightly Larger than Integrated Circuit Carrier (SLICC) (which issimilar to the BGA but has a smaller solder ball pitch and diameter thanthe BGA); a Pin Grid Array (PGA) (wherein an array of small pins extendssubstantially perpendicularly from the attachment surface of a flipchip, such that the pins conform to a specific arrangement on a printedcircuit board or other substrate for attachment thereto). With the BGAor SLICC, the solder or other conductive ball arrangement on the flipchip must be a mirror image of the connecting bond pads on the printedcircuit board so that precise connection can be made.

In creating semiconductor devices, the technology of interconnectingdevices and device features is a continuing challenge in the era ofsub-micron devices. Bond pads and solder bumps are frequently used forthis purpose, whereby continuous effort is dedicated to creating bondpads and solder bumps that are simple, reliable and inexpensive.

Bond pads are generally used to wire device elements and to provideexposed contact regions of the die. These contact regions are suitablefor wiring the die to components that are external to the die. Anexample is where a bond wire is attached to a bond pad of asemiconductor die at one end and to a portion of a Printed Circuit Boardat the other end of the wire. The art is constantly striving to achieveimprovements in the creation of bond pads that simplify themanufacturing process while enhancing bond pad reliability.

Materials that are typically used for bond pads include metallicmaterials, such as tungsten and aluminum, while heavily dopedpolysilicon can also be used for contacting material. The bond pad isformed on the top surface of the semiconductor device whereby theelectrically conducting material is frequently embedded in an insulatinglayer of dielectric. In using polysilicon as the bond pad material,polysilicon can be doped with an n-type dopant for contacting N-regionswhile it can be doped with p-type dopant for contacting P-regions. Thisapproach of doping avoids inter-diffusion of the dopants and dopantmigration. It is clear that low contact resistance for the bond pad areais required while concerns of avoidance of moisture or chemical solventabsorption, thin film adhesion characteristics, delamination andcracking play an important part in the creation of bond pads.

The conventional processing sequence that is used to create an aluminumbond pad starts with a semiconductor surface, typically the surface of asilicon single crystalline substrate. A layer of Intra Metal Dielectric(IMD) is deposited over the surface, a layer of metal, typicallyaluminum, is deposited over the surface of the layer of IMD. The layerof metal is patterned and etched typically using a layer of photoresistand conventional methods of photolithography and etching. After a bondpad has been created in this manner, a layer of passivation is depositedover the layer of IMD. An opening that aligns with the bond pad iscreated in the layer of passivation, again using methods ofphotolithography and etching.

A conventional method that is used to create a solder bump over acontact pad is next highlighted. FIGS. 1 through 4 show an example ofone of the methods that is used to create an interconnect bump. Asemiconductor surface 10 has been provided with a metal contact pad 14;the semiconductor surface 10 is protected with a layer 12 ofpassivation. An opening 19 has been created in the layer 12 ofpassivation; the surface of the metal contact pad 14 is exposed throughthis opening 19. Next, in FIG. 2, a dielectric layer 16 is depositedover the surface of the layer 12 of passivation. The layer 16 ofdielectric is patterned and etched, creating an opening 21 in the layer16 of dielectric that aligns with the metal pad 14 and that partiallyexposes the surface of the metal pad 14. A layer 18 of metal, typicallyusing Under-Bump-Metallurgy (UBM), is created over the layer 16 ofdielectric; layer 18 of metal is in contact with the surface of themetal pad 14 inside opening 21. The region of layer 18 of metal that isabove the metal pad 14 will, at a later point in the processing, form apedestal over which the interconnect bump will be formed. This pedestalcan be further extended in a vertical direction by the deposition andpatterning of one or more additional layers that may contain aphotoresist or a dielectric material; these additional layers are notshown in FIG. 2. These layers essentially have the shape of layer 16 andare removed during one of the final processing steps that is applied forthe formation of the interconnect bump.

A layer of photoresist (not shown) is deposited, patterned and etched,creating an opening that aligns with the contact pad 14. A layer 20 ofmetal, such as copper or nickel, shown in FIG. 3, that forms an integralpart of the pedestal of the to-be-created interconnect bump, is nextelectroplated in the opening created in the layer of photoresist and onthe surface of the layer 18 of metal, whereby the layer 18 serves as thelower electrode during the plating process. Layer 20 in prior artapplications has a thickness of between about 1 and 10 μm with a typicalvalue of about 5 μm. The final layer 22 of solder is electroplated onthe surface of layer 20. The patterned layer of photoresist is thenremoved.

The layer 18 of metal is next etched, as in FIG. 4, leaving in placeonly the pedestal for the interconnect bump. During this etch processthe deposited layers 20 and 22 serve as a mask. If, as indicated above,additional layers of dielectric or photoresist have been deposited forthe further shaping of pedestal 18 in FIG. 2, these layers are alsoremoved at this time.

A solder paste or flux (not shown) is now applied to the layer 22 ofsolder, and the solder 22 is melted in a reflow surface typically undera nitrogen atmosphere, creating the spherically shaped interconnect bump22 that is shown in FIG. 4.

In addition to the above indicated additional layers of dielectric orphotoresist that can be used to further shape the pedestal of theinterconnect bump, many of the applications that are aimed at creatinginterconnect bumps make use of layers of metal that serve as barrierlayers or that have other specific purposes, such as the improvement ofadhesion of the various overlying layers or the prevention of diffusionof materials between adjacent layers. These layers collectively formlayer 18 of FIG. 4 and have, as is clear from the above, an effect onthe shape of the completed bump and are therefore frequently referred toas Ball Limiting Metal (BLM) layer. Frequently used BLM layers aresuccessive and overlying layers of chrome, copper and gold, whereby thechrome is used to enhance adhesion with an underlying aluminum contactpad, the copper layer serves to prevent diffusion of solder materialsinto underlying layers, while the gold layer serves to prevent oxidationof the surface of the copper layer. The BLM layer is layer 18 of FIGS. 2through 4.

Increased device density brings with it increased closeness ofcomponents and elements that are part of the created semiconductordevices. This increased closeness is expressed as a reduction in thespacing or “pitch” between elements of a semiconductor device.State-of-the-art technology uses solder bumps having a pitch of about200 μm, which imposes a limitation on further increasing device density.The limitation in further reducing the pitch of solder bumps is imposedby concerns of reliability, which impose a relatively large ball sizefor the solder bump. This relatively large solder ball restricts furtherreducing the solder ball pitch.

In the majority of applications, solder bumps are used asinterconnections between I/O bond pads and a substrate or printedcircuit board. A large solder ball brings with it high standoff since asolder ball with high standoff has better thermal performance (CTEmismatching is easier to avoid resulting in reduced thermal stress onthe solder balls). Large solder balls are therefore required in order tomaintain interconnect reliability. Low-alpha solder is applied to avoidsoft error (electrical or functional errors) from occurring, therebyeliminating the potential for inadvertent memory discharge and incorrectsetting of the voltage (1 or 0).

U.S. Pat. No. 6,169,329 (Farnworth et al.) shows standardized die tosubstrate bonding locations (Ball grid or other array).

U.S. Pat. No. 5,741,726 (Barber) shows an assembly with minimized bondfinger connections.

U.S. Pat. No. 5,744,843 (Efland et al.), U.S. Pat. No. 5,172,471(Huang), U.S. Pat. No. 6,060,683 (Estrade), U.S. Pat. No. 5,643,830(Rostoker et al.), and U.S. Pat. No. 6,160,715 (Degani et al.) arerelated patents.

The invention addresses concerns of creating a BGA type package wherebythe pitch of the solder ball or solder bump of the device interconnectis in the range of 200 μm or less. The conventional, state-of-the-artsolder process runs into limitations for such a fine interconnect padpitch. The invention provides a method and a package for attachingdevices having very small ball pitch to an interconnect medium such as aPrinted Circuit Board.

SUMMARY OF THE INVENTION

A principal objective of the invention is to provide a method ofcreating a fine-pitch solder bump.

Another objective of the invention is to provide a method of creatingsmaller solder bumps, further allowing for the creation of fine-pitchedsolder bumps.

Another objective of the invention is to provide a cost-effective methodto create a fine-pitch solder bump of high reliability, due to theincreased height of the solder bump. This objective is based on thebelief that solder bump reliability improves proportionally to thesquare of the distance between the solder ball and the underlyingsubstrate.

Another objective of the invention is to provide a cost-effective way ofcreating a solder bump. This cost-effective way is realized by usingstandard solder material and therewith eliminating the need forexpensive “low-a solder”.

Another objective of the invention is to provide a cost-effective methodof creating a fine-pitch solder bump by reducing the alpha-effect onmemory products.

Another objective of the invention is to provide a method of creatingsolder bumps which allows an easy method of cleaning flux after theprocess of creating the solder bumps has been completed.

Another objective of the invention is to provide a method of creatingsolder bumps which allows easy application of underfill.

Another objective of the invention is to provide a method for applyingfine-pitch solder bumps directly to the I/O pads of a semiconductordevice, without a redistribution interface, and bonding thesemiconductor device directly to a Ball Grid Array substrate using theflip-chip bonding approach.

Another objective of the invention is to provide a method for shorteningthe interconnection between a semiconductor device and a substrate onwhich the semiconductor device is mounted, thus improving the electricalperformance of the semiconductor device.

Yet another objective of the invention is to eliminate conventionalmethods of re-distribution of device I/O interconnect, thereby makingpackaging of the device more cost-effective and eliminating performancedegradation.

A still further objective of the invention is to improve chipaccessibility during testing of the device, thus eliminating the needfor special test fixtures.

A still further objective of the invention is to improve performance anddevice reliability of BGA packages that are used for the mounting ofsemiconductor devices having small-pitch I/O interconnect bumps.

A still further objective of the invention is to perform Chip ScalePackaging (CSP) without re-distribution, including for various paddesigns such as peripheral or central pad designs.

A still further objective of the invention is to provide a method ofmounting small-pitch semiconductor devices in such a manner that fluxremoval and the dispensing of device encapsulants is improved.

In accordance with the objectives of the invention, a new method andpackage is provided for the mounting of semiconductor devices that havebeen provided with small-pitch Input/Output interconnect bumps. Finepitch solder bumps, consisting of pillar metal and a solder bump, areapplied directly to the I/O pads of the semiconductor device, and thedevice is then flip-chip bonded to a substrate. Dummy bumps may beprovided for cases where the I/O pads of the device are arranged suchthat additional mechanical support for the device is required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 4 show a prior-art method of creating a solder bumpoverlying a point of electrical contact, as follows:

FIG. 1 shows a cross section of a semiconductor surface on the surfaceof which a contact pad has been created; the semiconductor surface iscovered with a patterned layer of passivation.

FIG. 2 shows a cross section of FIG. 1 after a patterned layer ofdielectric and a layer of metal have been created on the semiconductorsurface.

FIG. 3 shows a cross section of FIG. 2 after a layer of bump metal andsolder compound have been selectively deposited.

FIG. 4 show a cross section that after excessive layers have beenremoved from the semiconductor surface and after the solder has beenreflowed, the interconnect bump is formed.

FIG. 5 shows a cross section of a BGA package; a semiconductor device isencapsulated in a molding compound.

FIG. 6 shows a cross section of a BGA package; an underfill is providedto the semiconductor device.

FIGS. 7 through 16 address the invention, as follows:

FIG. 7 shows a cross section of a semiconductor surface, a layer ofdielectric, metal pads, a layer of passivation, and a layer of barriermaterial.

FIG. 8 shows a cross section after a patterned layer of photoresist hasbeen created over the structure of FIG. 7.

FIG. 9 shows a cross section after pillar metal has been created alignedwith the metal pads and under bump metal has been deposited over thesurface of the pillar metal.

FIG. 10 shows a cross section after solder metal has been plated overthe under bump metal.

FIG. 11 shows a cross section after the patterned layer of photoresisthas been removed from the surface.

FIG. 12 shows a cross section after the diameter of the pillar metal hasbeen reduced.

FIG. 13 shows a cross section after the barrier layer has been etchedusing isotropic etching, creating a first profile.

FIG. 14 shows a cross section after the barrier layer has been etchedusing anisotropic etching or RIE, creating a second profile.

FIG. 15 shows a cross-section of a first completed solder bump of thepresent invention.

FIG. 16 shows a cross-section of a second completed solder bump of thepresent invention.

FIG. 17 shows a cross section of a BGA package of the invention; thesemiconductor device is encapsulated in a molding compound.

FIG. 18 shows a cross section of a BGA package of the invention; anunderfill is provided to the semiconductor device.

FIG. 19 shows a top view of an array type I/O pad configuration of thesemiconductor device.

FIG. 20 shows a top view of a peripheral type I/O pad configuration ofthe semiconductor device.

FIG. 21 shows a top view of a center type I/O pad configuration of thesemiconductor device.

FIG. 22 shows a top view of a center type I/O pad configuration of thesemiconductor device; dummy solder bumps have been provided in supportof the semiconductor device.

FIG. 23 shows a top view of the substrate with exposed I/O contact pads;this exposure is accomplished by not depositing the solder mask in closeproximity to the contact pads of the semiconductor device.

FIG. 24 shows a cross section of the substrate of FIG. 23.

FIG. 25 shows a top view of a prior-art substrate with exposed I/Ocontact pads; a solder mask is in close proximity to the contact pads ofa semiconductor device.

FIG. 26 shows a cross section of the substrate of FIG. 25.

FIGS. 27 a through 27 f show examples of applications of the invention.

FIGS. 28 a and 28 b show a conventional substrate and a substrate of theinvention and demonstrate how the invention leads to the ability toreduce the pitch between I/O pads.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The above stated objective of improving chip accessibility duringtesting of the device, thus eliminating the need for special testfixtures, can further be highlighted as follows. The disclosed method ofthe invention, using Chip Scale Packaging (CSP), can control the cost oftesting CSP devices by keeping the same body size of the chip and byusing the same size substrate. For conventional CSP packages, the chipmay have different body sizes, which imposes the requirement ofdifferent size test fixtures. With the continued reduction of the sizeof semiconductor devices, additional and varying device sizes areexpected to be used. This would result in ever increasing costs forback-end testing of the devices in a production environment. Theinvention provides a method where these additional back-end testingcosts can be avoided.

Referring now to FIG. 5, there is shown a cross section of a typicalflip chip package with a semiconductor device being encapsulated in amolding compound. An Integrated Circuit (IC) device 10 enters theprocess as a separate unit with contact points (balls 16) attached tothe bottom of the chip 10. The IC 10 is placed on the surface of a BGAsubstrate 12, and an (optional) interconnect substrate 14 has beenprovided for additional routing of the electrical network to which thedevice 10 is attached. Balls 18 that are connected to the lower surfaceof the substrate 12 make contact with surrounding circuitry (not shown).The paths of electrical interconnect of the device 10 as shown in crosssection in FIG. 5 are as follows: contact bumps (points of I/Ointerconnect, not shown in FIG. 5) are provided on the surface of thedevice that faces the substrate 12 and the contact balls 16 areconnected to these contact bumps. Contact balls 16 interface with pointsof contact (contact pads) provided in the surface of the (optional)interconnect network 14 or, for applications where the interconnectinterface 14 is not provided, with points of contact (contact pads)provided in the surface of the Ball Grid Array (BGA) substrate 12. BGAsubstrate 12 may further have been provided with one or more layers ofinterconnect metal; all of the interfaces (the interconnect substrate 12and the optional redistribution lines provided in BGA substrate 12)result in interconnecting balls 16 with the balls 18. The Balls 18 arethe contact points that connect the package that is shown in crosssection in FIG. 5 to surrounding circuitry.

Whereas the cross section that is shown in FIG. 5 shows the contactballs 16 for the establishment of contacts between the device 10 and theunderlying substrate 12, some prior art applications still used wirebond connections (not shown in FIG. 5), in order to achieve optimumelectrical performance of the device package.

Further shown in the cross section of FIG. 5 is layer 19, which may beprovided over the surface of the semiconductor device 10 facing thesubstrate 12. This re-distribution layer provides interconnect linesover the surface of the device 10 and is required in prior artapplications if solder bumps are required on current pad layout for wirebonding purposes. The main purpose of the redistribution layer is toenlarge the pitch of solder bump interconnects if the bond pads areoriginally designed for wire bonding applications. It will be clear fromlater explanations that the invention removes the need for theredistribution layer.

FIG. 6 shows a cross section of a conventional BGA package whereby thesemiconductor device 10 is provided with underfill 22, and no moldingcompound (20, FIG. 5) has been provided in the package that is shown incross section in FIG. 6. All the other statements that relate to theelectrical interconnection of the device 10 of FIG. 6 are identical tothe statements that have been made in the description provided for thepackage of FIG. 5. It should be noted in FIG. 6 that the sides of theunderfill 22 are sloping such that the physical contact between theunderfill 22 and the substrate 12 is extended beyond the dimensions ofthe bottom surface of the chip 10. This is a normal phenomenon withliquid underfill, which enhances the mechanical strength between thesubstrate 12 and the IC chip 10.

Referring now to FIG. 15, there is shown a cross section of a firstsolder bump that has been created in accordance with the abovereferenced related application. The elements that are shown in FIG. 15that form part of the solder bump of the related application are thefollowing:

-   -   10, a semiconductor surface such as the surface of a substrate,    -   30, a layer of dielectric that has been deposited over the        semiconductor surface 10,    -   32, contact pads that have been created on the surface of the        layer 30 of dielectric,    -   34, a patterned layer of passivation that has been deposited        over the surface of the layer 30 of dielectric; openings have        been created in the layer 34 of passivation, partially exposing        the surface of the contact pads 32,    -   36, an isotropically etched layer of barrier metal; this layer        of barrier metal has been isotropically etched; that is, the        barrier metal has been completely removed from the surface of        the layer 34 of passivation except where the barrier metal is        covered by overlying pillar metal (38) of a solder bump,    -   38, the pillar metal of the solder bump,    -   40, a layer of under bump metal created overlying the pillar        metal 38 of the solder bump, wherein a horizontal distance        between an edge of the under bump metal layer 40 and an edge of        the metal pillar 38 of the solder bump is greater than 0.2        micrometers, wherein the layer 40 of under bump metal is an        electroplated nickel layer with a thickness between 1 and 10        micrometers, and    -   42, a solder metal.

The cross section that is shown in FIG. 16 is similar to the crosssection of FIG. 15 with the exception of layer 35, which is ananisotropically etched layer of barrier metal (etched after the solderbump 42 has been created) which, due to the nature of the anisotropicetch, protrudes from the pillar metal 38 as shown in the cross sectionof FIG. 16.

The cross sections that are shown in FIGS. 15 and 16 and that have beenextracted from the above referenced related application have been shownin order to highlight that the referenced application provides a methodof creating:

a fine-pitch solder bump,

smaller solder bumps,

a fine-pitch solder bump of high reliability due to the increased heightof the solder bump,

a cost-effective solder bump by using standard solder material andeliminating the need for expensive “low-a solder”,

a solder bump that allows easy cleaning of flux after the process offlip chip assembly and before the process of underfill andencapsulation, and

a solder bump which allows easy application of underfill.

FIGS. 7 through 16 provide details of the process of the invention whichleads to the solder bumps that have been shown in cross section in FIGS.5 and 6.

FIG. 7 shows a cross section of a substrate 10 and the followingelements:

-   -   10, a silicon substrate over the surface of which metal contact        pads 32 have been created,    -   30, a layer of dielectric that has been deposited over the        surface of the substrate 10,    -   32, the metal contact pads, typically comprising aluminum,        created over the surface of the layer 30 of dielectric,    -   34, a layer of passivation that has been deposited over the        surface of the layer 30 of dielectric. Openings have been        created in the layer 34 of passivation that align with the metal        contact pads 32, partially exposing the surface of the contact        pads 32,    -   36, a layer of barrier metal that has been created over the        surface of the layer 34 of passivation, including the openings        that have been created in the layer 34 of passivation,        contacting the underlying contact pads 32.

As dielectric material for the layer 30 can be used any of the typicallyapplied dielectrics such as silicon dioxide (doped or undoped), siliconoxynitride, parylene, polyimide, spin-on-glass, plasma oxide or LPCVDoxide. The material that is used for the deposition of the layer 30 ofdielectric of the invention is not limited to the materials indicatedabove, but can include any of the commonly used dielectrics in the art.

The creation of the metal contact pads 32 can use conventional methodsof metal rf sputtering at a temperature between about 100 and 400degrees C. and a pressure between about 1 and 100 mTorr using as source,for instance, aluminum-copper material (for the creation of aluminumcontact pads) at a flow rate of between about 10 and 400 sccm to athickness between about 4000 and 11000 Angstroms. After a layer of metalhas been deposited, the layer must be patterned and etched to create thealuminum contact pads 32. This patterning and etching uses conventionalmethods of photolithography and patterning and etching. A depositedlayer of AICu can be etched using Cl₂/Ar as an etchant at a temperaturebetween 50 and 200 degrees C., an etchant flow rate of about 20 sccm forthe Cl₂ and 1000 sccm for the Ar, a pressure between about 50 mTorr and10 Torr, and a time of the etch between 30 and 200 seconds.

In a typical application, insulating layers, such as silicon oxide andoxygen-containing polymers, are deposited using a Chemical VaporDeposition (CVD) technique over the surface of various layers ofconducting lines in a semiconductor device or substrate to separate theconductive interconnect lines from each other. The insulating layers canalso be deposited over patterned layers of interconnecting lines;electrical contact between successive layers of interconnecting lines isestablished with metal vias created in the insulating layers. Electricalcontact to the chip is typically established by means of bonding pads orcontact pads that form electrical interfaces with patterned levels ofinterconnecting metal lines. Signal lines and power/ground lines can beconnected to the bonding pads or contact pads. After the bonding pads orcontact pads have been created on the surfaces of the chip, the bondingpads or contact pads are passivated and electrically insulated by thedeposition of a passivation layer over the surface of the bonding pads.A passivation layer can contain silicon oxide/silicon nitride(SiO₂/Si₃N₄) deposited by CVD. The passivation layer is patterned andetched to create openings in the passivation layer for the bonding padsor contact pads after which a second and relatively thick passivationlayer can be deposited for further insulation and protection of thesurface of the chips from moisture and other contaminants and frommechanical damage during assembling of the chips.

Various materials have found application in the creation of passivationlayers. The passivation layer can contain silicon oxide/silicon nitride(SiO₂/Si₃N₄) deposited by CVD, or a passivation layer can be a layer ofphotosensitive polyimide or can comprise titanium nitride. Anothermaterial often used for a passivation layer is phosphorous doped silicondioxide that is typically deposited over a final layer of aluminuminterconnect using a Low Temperature CVD process. In recent years,photosensitive polyimide has frequently been used for the creation ofpassivation layers. Conventional polyimides have a number of attractivecharacteristics for their application in a semiconductor devicestructure which have been highlighted above. Photosensitive polyimideshave these same characteristics but can, in addition, be patterned likea photoresist mask and can, after patterning and etching, remain on thesurface on which it has been deposited to serve as a passivation layer.Typically and to improve surface adhesion and tension reduction, aprecursor layer is first deposited by, for example, conventionalphotoresist spin coating. The precursor is, after a low temperaturepre-bake, exposed using, for example, a step and repeat projectionaligner and Ultra Violet (UV) light as a light source. The portions ofthe precursor that have been exposed in this manner are cross-linked,thereby leaving unexposed regions (that are not cross-linked) over thebonding pads. During subsequent development, the unexposed polyimideprecursor layer (over the bonding pads) is dissolved, thereby providingopenings over the bonding pads. A final step of thermal curing leaves apermanent high quality passivation layer of polyimide over thesubstrate.

The preferred material of the invention for the deposition of the layer34 of passivation is Plasma Enhanced silicon nitride (PE Si₃N₄),deposited using PECVD technology at a temperature between about 350 and450 degrees C. with a pressure of between about 2.0 and 2.8 Torr for theduration between about 8 and 12 seconds. The layer 34 of PE Si₃N₄ can bedeposited to a thickness between about 200 and 800 Angstroms.

The layer 34 of PE Si₃N₄ is next patterned and etched to create openingsin the layer 34 that overlay and align with the underlying contact pads32.

The etching of the layer 34 of passivation can use Ar/CF₄ as an etchantat a temperature of between about 120 and 160 degrees C. and a pressureof between about 0.30 and 0.40 Torr for a time of between about 33 and39 seconds using a dry etch process.

The etching of the layer 34 of passivation can also use He/NF₃ as anetchant at a temperature of between about 80 and 100 degrees C. and apressure of between about 1.20 and 1.30 Torr for a time of between about20 and 30 seconds using a dry etch process.

Barrier layers, such as the layer 36, are typically used to preventdiffusion of an interconnect metal into surrounding layers of dielectricand silicon. Some of the considerations that apply in selecting amaterial for the barrier layer become apparent by using copper forinterconnect metal as an example. Although copper has a relatively lowcost and low resistivity, it has a relatively large diffusioncoefficient into silicon dioxide and silicon and is therefore nottypically used as an interconnect metal. Copper from an interconnect maydiffuse into the silicon dioxide layer causing the dielectric to beconductive and decreasing the dielectric strength of the silicon dioxidelayer. Copper interconnects should be encapsulated by at least onediffusion barrier to prevent diffusion into the silicon dioxide layer.Silicon nitride is a diffusion barrier to copper, but the prior artteaches that the interconnects should not lie on a silicon nitride layerbecause it has a high dielectric constant compared with silicon dioxide.The high dielectric constant causes an undesired increase in capacitancebetween the interconnect and the substrate.

A typical diffusion barrier layer may contain silicon nitride,phosphosilicate glass (PSG), silicon oxynitride, aluminum, aluminumoxide (Al_(x)O_(y)), tantalum, Ti/TiN or Ti/W, nionbium, or molybdenumand is more preferably formed from TiN. The barrier layer can also beused to improve the adhesion of the subsequent overlying tungsten layer.

The barrier layer is preferably between about 500 and 2000 Angstromsthick and more preferably about 300 Angstroms thick, and can bedeposited using rf sputtering.

After the creation of the barrier layer 36, a seed layer (not shown inFIG. 7) can be blanket deposited over the surface of the wafer. For aseed layer that is blanket deposited over the surface of the wafer, anyof the conventional metallic seed materials can be used. The metallicseed layer can be deposited using a sputter chamber or an Ion MetalPlasma (IMP) chamber at a temperature of between about 0 and 300 degreesC. and a pressure of between about 1 and 100 mTorr, using (for instance)copper or a copper alloy as the source (as highlighted above) at a flowrate of between about 10 and 400 sccm and using argon as an ambient gas.

FIG. 8 shows a cross section of the substrate after a layer 37 ofphotoresist has been deposited over the surface of the barrier layer 36.The layer 37 of photoresist has been patterned and etched, creatingopenings 31 in the layer 37 of photoresist. The openings 31 partiallyexpose the surface of the barrier layer 36. The layer 37 of photoresistis typically applied to a thickness of between about 100 and 200 μm, butmore preferably to a thickness of about 150 μm.

The methods used for the deposition and development of the layer 37 ofphotoresist uses conventional methods of photolithography.Photolithography is a common approach wherein patterned layers areformed by spinning on a layer of photoresist, projecting light through aphotomask with the desired pattern onto the photoresist to expose thephotoresist to the pattern, developing the photoresist, washing off theundeveloped photoresist, and plasma etching to clean out the areas wherethe photoresist has been washed away. The exposed resist may be renderedsoluble (positive working) and washed away, or insoluble (negativeworking) and form the pattern.

The deposited layer 37 of photoresist can, prior to patterning andetching, be cured or pre-baked, further hardening the surface of thelayer 37 of photoresist.

The layer 37 of photoresist can be etched by applying O₂ plasma and thenwet stripping by using H₂SO₄, H₂O₂ and NH₄OH solution. Sulfuric acid(H₂SO₄) and mixtures of H₂SO₄ with other oxidizing agents such ashydrogen peroxide (H₂O₂) are widely used in stripping photoresist afterthe photoresist has been stripped by other means. Wafers to be strippedcan be immersed in the mixture at a temperature between about 100degrees C. and about 150 degrees C. for 5 to 10 minutes and thensubjected to a thorough cleaning with deionized water and dried by drynitrogen. Inorganic resist strippers, such as the sulfuric acidmixtures, are very effective in the residual free removal of highlypostbaked resist. They are more effective than organic strippers and thelonger the immersion time, the cleaner and more residue-free wafersurface can be obtained.

The photoresist layer 37 can also be partially removed using plasmaoxygen ashing and careful wet clean. The oxygen plasma ashing is heatingthe photoresist in a highly oxidized environment, such as an oxygenplasma, thereby converting the photoresist to an easily removed ash. Theoxygen plasma ashing can be followed by a native oxide dip for 90seconds in a 200:1 diluted solution of hydrofluoric acid.

FIG. 9 shows a cross section of the substrate 10 after a layer 38 ofpillar metal has been deposited (electroplated) over the surface of thelayer 36 of barrier material and bounded by openings 31 that have beencreated in the layer 37 of photoresist. Over the surface of the layers38 of metal, which will be referred to as pillar metal in view of therole these layers play in the completed structure of the solder bumps ofthe invention, layers 40 of under bump metal have been deposited usingdeposition methods such as electroplating.

The layer 36 preferably comprises titanium or copper and is preferablydeposited to a thickness of between about 500 and 2000 Angstroms, andmore preferably to a thickness of about 1000 Angstroms.

The layer 38 preferably comprises copper and is preferred to be appliedto a thickness of between about 10 and 100 μm, but more preferably to athickness of about 50 μm.

The layer 40 preferably comprises nickel and is preferred to be appliedto a thickness of between about 1 and 10 μm, but more preferably to athickness of about 4 μm.

FIG. 10 shows a cross section where the process of the invention hasfurther electroplated layers 42 of solder metal over the surface of thelayers 40 of under bump metal (UBM) and bounded by the openings 31 thathave been created in the layer 37 of photoresist.

The layer 40 of UBM, typically of nickel and of a thickness betweenabout 1 and 10 μm, is electroplated over the layer 38 of pillar metal.The layer 42 of bump metal (typically solder) is electroplated incontact with the layer 40 of UBM to a thickness of between about 30 and100 μm, but more preferably to a thickness of about 50 μm. The layers38, 40 and 42 of electroplated metal are centered in the opening 31 thathas been created in the layer 37 of photoresist.

In the cross section that is shown in FIG. 11, it is shown that thepatterned layer 37 of photoresist has been removed from above thesurface of the barrier layer 36. The previously highlighted methods andprocessing conditions for the removal of a layer of photoresist can beapplied for the purpose of the removal of the layer 37 that is shown incross section in FIG. 11. The invention further proceeds with thepartial etching of the pillar metal 38, as shown in cross section inFIG. 12, using methods of wet chemical etching or an isotropic dry etch,selective to the pillar metal material. It is clear that, by adjustingthe etching parameters, of which the time of etch is most beneficial,the diameter of the pillar metal 38 can be reduced by almost any desiredamount. The limitation that is imposed on the extent to which thediameter of the pillar metal 38 is reduced is not imposed by the wetetching process, but by concerns of metal bump reliability andfunctionality. Too small a remaining diameter of the pillar metal 38will affect the robustness of the solder bumps while this may also havethe effect of increasing the resistance of the metal bump.

The final two processing steps of the invention, before the solder metalis reflowed, are shown in the cross section of FIGS. 13 and 14 andaffect the etching of the exposed surface of the barrier layer 36. Usingisotropic etching, the exposed barrier layer 36 is completely removed asshown in FIG. 13. Using anisotropic etching, in FIG. 14, the etching ofthe barrier layer 36 is partially impeded by the presence of the columns42 of solder metal.

It is believed that the undercut shape of the pillar 38 will preventwetting of the pillar 38 and the UBM layer 40 during subsequent solderreflow. It is also believed that exposure to air will oxidize thesidewalls of the pillar 38 and the UBM layer 40 and therefore preventwetting of these surfaces during subsequent solder reflow. Optionally,the sidewalls of the pillar 38 and the UBM layer 40 may be furtheroxidized by, for example, a thermal oxidation below reflow temperatureof about 240 degrees C. such as heating in oxygen ambient at about 125degrees C.

FIGS. 15 and 16 show the final cross section of the solder bump of theinvention after the solder metal has been reflowed. FIG. 15 correspondsto FIG. 13 while FIG. 16 corresponds to FIG. 14, this relating to theetch in the barrier layer 36 that has been explained using FIGS. 13 and14. It is noted that the etched layer 36 of barrier material that isshown in cross section in FIG. 15 corresponds to the etched layer 36 ofbarrier material that is shown in FIG. 13. The same correspondenceexists between FIGS. 16 and 14.

The above summarized processing steps of electroplating that are usedfor the creation of a metal bump can be supplemented by the step ofcuring or pre-baking of the layer of photoresist after this layer hasbeen deposited.

To review and summarize the invention:

-   -   prior to and in preparation for the invention, a semiconductor        surface is provided, a layer of dielectric has been deposited        over the semiconductor surface, a contact pad has been provided        on the layer of dielectric, the contact pad has an exposed        surface, a layer of passivation has been deposited over a        semiconductor surface including the surface of said contact pad,        and the layer of passivation has been patterned and etched,        creating an opening in the layer of passivation, partially        exposing the surface of the contact pad, the opening in the        layer of passivation is centered with respect to the contact pad    -   the invention starts with a barrier layer deposited over the        surface of the layer of passivation, making contact with the        contact pad through the opening created in the layer of        passivation    -   a layer of photoresist is deposited over the surface of the        barrier layer    -   the layer of photoresist is patterned and etched, creating an        opening through the layer of photoresist, wherein the opening in        the layer of photoresist aligns with and is centered with        respect to the contact pad    -   in sequence are deposited, bounded by the opening created in the        layer of photoresist, a layer of pillar metal, a layer of under        bump metal and a layer of solder metal    -   the patterned layer of photoresist is removed from the surface        of the barrier layer    -   the layer of pillar metal is etched, reducing the diameter of        the pillar metal    -   the barrier layer is etched, using either isotropic or        anisotropic etching    -   the solder metal is reflowed.

The invention offers the following advantages:

-   -   ball height is a very important reliability concern; in order to        prevent thermal mismatch between overlying layers of a package        (such as a semiconductor device and an underlying printed        circuit board and the like), it is important to increase the        distance between overlying elements; the invention provides this        ability,    -   a larger solder ball (for better thermal or reliability        performance) results in increased pitch; this is contrary to        state of the art design requirements,    -   if small solder balls are used without providing height, it is        very difficult to underfill the small gaps,    -   the solder is, using the invention, relatively far removed from        the semiconductor device which means that the application of        low-alpha solder is not required (alpha-particles create soft        errors in memory products; lead is known to emit alpha-particles        when lead decays),    -   for the pillar metal, a metal needs to be selected that has good        conductivity and good ductility, such as copper. This is in        order to provide improved thermal performance by counteracting        thermal stress,    -   the height of the pillar of the solder bump of the invention is        important and should be between about 10 to 100 μm in order to        achieve objectives of high stand-off, and    -   the metal that is used for the under bump metal layer is        important in that this metal must have good adhesion with the        overlying solder during solder reflow while this metal must not        solve too fast and in so doing form a barrier to the solder; in        addition, the UBM metal when exposed to air can form a layer of        protective oxide thus preventing solder wetting to the pillar        metal around the perimeter of the UBM metal during the reflow        process; nickel is therefore preferred for the UBM metal.

Now the packaging of the invention using the solder bumps describedabove will be discussed. Referring now to the cross section that isshown in FIG. 17, there is shown a cross section of a BGA package of theinvention whereby the semiconductor device has been encapsulated in amolding compound. The elements that are highlighted in the cross sectionof FIG. 17 are the following:

-   -   50, a semiconductor device that is mounted in the package of the        invention shown in the cross section in FIGS. 17,    -   52, a (BGA) substrate on the surface of which the device 50 is        mounted,    -   54, a pillar metal of the interface between the device 50 and        the BGA substrate 52, similar to the pillar metal 38 of FIGS. 15        and 16, wherein the pillar metal 38 or 54 is an electroplated        copper layer with a thickness between 10 and 100 micrometers,    -   56, a solder bump of the interface between the device 50 and the        BGA substrate 52, similar to the solder bump 42 of FIGS. 15 and        16,    -   58, contact balls that are used to interconnect the package of        the invention with surrounding circuitry, and    -   60, molding compound into which the device 50 is embedded for        protection against the environment.

The columns 54 of pillar metal typically have a height of between about10 and 100 μm, and more preferably about 50 μm.

The cross section that is shown in FIG. 18 is identical to the crosssection of FIG. 17, with the exception of an underfill 62 which is usedinstead of the molding compound 60 of FIG. 17.

The following comment applies: the creation of the pillar metal 54 andthe solder bump 56 starts using the I/O contact pads of the device 50(not shown in FIGS. 17 and 18) as the contact pads; that is the I/Ocontact pads of the device 50 take the place of the contact pad 32 ofFIGS. 15 and 16 in the creation of the pillar metal 54 and the solderbump 56. The process of creating the pillar metal 54 and the solder bump56 therefore is as follows:

-   -   a layer of dielectric is deposited over an active surface of the        device 50; the active surface of the device 50 is the surface in        which I/O contact points have been provided; this surface will        face the BGA substrate 52 after mounting of the device 50 on the        BGA substrate 52,    -   openings are created in the layer of dielectric, exposing the        I/O contact pads of the device 50; this brings the process of        the invention to the point of the related application where the        contact pads 32 (FIGS. 15, 16) have been created on the surface        of the layer 30 of dielectric,    -   a layer of passivation is deposited over the surface of the        layer of dielectric, similar to the layer 34, FIGS. 15, 16,    -   openings are created in the layer of passivation, partially        exposing the surface of the device I/O contact pads,    -   a barrier layer is deposited over the surface of the layer of        passivation, identical to the layer 36, FIGS. 15, 16,    -   the pillar metal 54 of the solder bump is formed, identical to        the layer 38, FIGS. 15, 16,    -   the layer of under bump (not shown in FIGS. 17, 18) is created        overlying the pillar metal 54, identical to the layer 40, FIGS.        15, 16,    -   the solder bump 56 is formed, identical to the layer 42, FIGS.        15, 16, and    -   the layer of barrier metal is isotropically (FIG. 15) or        anisotropically (FIG. 16) etched.

Referring now to FIG. 19, there is shown a top view of an array typearrangement of I/O contact points 66 that form the contact points of thedevice 50. This top view of the array type contact points 66 is shown asone example of where the process of creating pillar metal and solderbumps can be applied.

FIGS. 20 and 21 show two more examples of arrangements of I/O contactpads that are provided on the surface of the device 50, where theprocess of the invention can be applied. FIG. 20 shows a peripheral I/Opad design 68 while FIG. 21 shows a center type pad design 70.

While the peripheral I/O pad design 68 that is shown in FIG. 20 providesevenly distributed mechanical support for the device 50, this is not thecase for the center pad design 70 that is shown in FIG. 21. For thiskind of design, additional mechanical support can be provided to thedevice 50; this is shown in a top view in FIG. 22. The elementshighlighted as 70 in FIG. 22 are the solder bumps that have been createdon the I/O contact pads of the device 50; elements 72 are dummy solderbumps that can be provided in order to lend mechanical support to thedevice 50. The symmetry of the dummy bumps 72 as shown in FIG. 22 makesclear that the device 50 is, with the dummy bumps 72, adequately andsymmetrically supported.

In mounting semiconductor devices on the surface of a BGA substrate, itis important from a manufacturing point of view that solder flux, afterthe process of the solder flow has been completed, can be readilyremoved. This requires easy access to the surface areas of the BGAsubstrate where the solder flux has been able to accumulate. Inaddition, the device interconnects (consisting of pillar metal andsolder bumps) must, after the pillar metal and the solder bumps havebeen formed in accordance with the related application, be readilyavailable so that device encapsulants can be adequately applied. Moreimportantly, after flip-chip assembly and solder reflow, the flux thathas accumulated in the gap between the semiconductor die and thesubstrate must be cleaned. For these reasons, it is of value to applythe solder mask not across the entire surface of the substrate (blankdeposition) but to leave open the surface areas of the substrate thatare immediately adjacent to the I/O interconnects (of pillar metal andsolder bumps). This design will create a channel though which thecleaning solution can flow easily. This is highlighted in a top view ofFIGS. 23 and 24, where is shown:

-   -   52, the BGA substrate on the surface of which the device 50 (not        shown) is mounted,    -   74, I/O contact pads provided on the surface of the substrate        52,    -   76, interconnect traces provided on the surface of the substrate        52, connected with the contact pads 74,    -   79, the surface region of the substrate 52 over which no solder        mask is applied, and    -   80, the surface region of the substrate 52 over which a solder        mask is applied.

This is further highlighted in the cross section of the substrate 52that is shown in FIG. 24. It is clear that over the region 79, which isthe region where no solder mask is applied, the metal pads 74 arereadily available so that removal of solder flux and the dispensing ofencapsulants can be performed. It must be remembered that this ispossible due to the height of the combined pillar metal 54 and thesolder bump 56, which results in adequate spacing between the device 50and the surface of the substrate 52. Further shown in FIG. 24 arerouting traces 82 that are provided on the surface of the substrate 52for additional interconnect.

FIGS. 25 and 26 show how prior-art procedures and conventions areapplied to affect flux removal and encapsulant application. In theprior-art application, the metal pads 74 are typically surrounded by thesolder mask 78, even for small pitch I/O pad designs. Typically, thesolder mask is determined by the type of contact pad design (FIGS. 19through 21), whereby the contact pads 74 require about 60 μm clearancefor reasons of proper alignment registration. This results in thesubstrate design rule being more critical, allowing for less error andsmaller tolerance in the design parameters. In addition, the height ofthe solder mask 78 is generally about 10μm larger than the height of thecontact pad 74, further forming an obstacle in applying molding compoundor in removing flux after the solder process has been completed. Theseaspects of the prior art are shown in FIGS. 25 and 26, where the metalpads 74 are completely surrounded by the solder mask 78. The presentinvention negates the highlighted negative effects of the solder mask onflux cleaning and on dispensing molding compound.

FIGS. 27 a through 27 f show examples of applications of the invention,as follows:

FIG. 27 a shows the application of a solder mask over the surface thathas previously been shown in FIG. 19, the solder mask has been indicatedwith cross-hatched regions 90, and the regions where no solder mask ispresent have been highlighted with 91.

FIGS. 27 b and 27 c relate to the previous FIG. 20, and the solder maskhas been highlighted as regions 90 while the regions where no soldermask is present have been highlighted with 91. The design that is shownin FIG. 27 c is considered a “partial” peripheral type I/O padconfiguration of a semiconductor device since the I/O pads 68 are onlyprovided along two opposing sides of the semiconductor device 50.

It must be noted that the designs that are shown in FIGS. 27 b and 27 ccan further be provided with supporting dummy solder bumps in theregions of the solder mask 90, and these supporting dummy solder bumpshave not been shown in FIGS. 27 b and 27 c.

FIG. 27 d shows the design that has previously been shown in FIG. 21.FIG. 27 e shows a design that is similar to the design of FIG. 27 d withthe exception that the contact points 70 have now been provided in twocolumns. It is clear from these two drawings that channels have beencreated in the solder mask 90 that are in line with and include thecontact pads. These channels allow for easy flow of cleaning fluid andtherefore allow for easy removal of solder flux after the process ofchip encapsulation and solder flow has been completed.

FIG. 27 f relates to the previously shown FIG. 22, and the aboveobservation relating to the creation of a channel allowing for easyremoval of the solder flux and for the easy flow of cleaning fluidequally applies to the design, which is shown in FIG. 27 f.

FIGS. 28 a and 28 b demonstrate how the invention leads to the abilityto reduce the pitch between I/O pads.

FIG. 28 a shows how in prior art applications the solder mask 90 isprovided, further shown in FIG. 28 a are:

-   -   94, the circumference of the opening that is created in the        solder mask 90,    -   95, the circumference of the bond pad on the surface of a        semiconductor device,    -   92, the distance (or spacing) S between two adjacent contact        pads, and    -   93, the diameter D of a contact pad.

In prior art applications as shown in FIG. 28 a, the pitch betweenadjacent contact pads is P=D+S+2×(the required clearance betweenadjacent contact pads). The required clearance is needed by the soldermask and requires that extra space is provided between the circumference95 of the contact pad and the circumference 94 of the opening created inthe solder mask.

With the wide channel created by the invention through the solder mask,highlighted as a channel 91 in FIG. 28 b, the conventional clearance isnot required, resulting in the ability to reduce the pitch betweenadjacent contact pads 95. This leads to a distance 92′, FIG. 28 b, whichis smaller than the distance 92 of FIG. 28 a.

Although the invention has been described and illustrated with referenceto specific illustrative embodiments thereof, it is not intended thatthe invention be limited to those illustrative embodiments. Thoseskilled in the art will recognize that variations and modifications canbe made without departing from the spirit of the invention. It istherefore intended to include within the invention all such variationsand modifications which fall within the scope of the appended claims andequivalents thereof.

1. A chip package comprising: a substrate; a semiconductor device oversaid substrate, wherein said semiconductor device comprises a siliconsubstrate, a dielectric layer under said silicon substrate, a firstmetal layer under said dielectric layer, wherein said first metal layercomprises a metal pad and a metal piece separate from said metal pad andneighboring said metal pad, and a polymer layer under said dielectriclayer, under said metal pad, under said metal piece and in a gap betweensaid metal pad and said metal piece, wherein an opening in said polymerlayer is under a first contact point of said metal pad, and said firstcontact point is at a top of said opening; a copper pillar between saidfirst contact point and said substrate, wherein said copper pillar has aheight between 10 and 100 micrometers, and wherein said copper pillar isconnected to said first contact point through said opening; a secondmetal layer between said first contact point and said copper pillar,wherein said second metal layer is on said first contact point, on abottom surface of said polymer layer and in said opening, wherein saidbottom surface has a first region directly over said second metal layerand directly under said metal pad and a second region directly under themiddle of said gap, wherein said first region is at a substantially samehorizontal level as said second region, and there is no significant stepbetween said first region and said second region, and wherein saidcopper pillar is connected to said first contact point through saidsecond metal layer; a solder between said copper pillar and saidsubstrate, wherein said solder is joined with said substrate, andwherein said solder is connected to said copper pillar; and an underfillbetween said semiconductor device and said substrate, wherein saidunderfill contacts with said semiconductor device and said substrate andencloses said copper pillar.
 2. The chip package of claim 1 furthercomprising a nickel-containing layer between said solder and said copperpillar.
 3. The chip package of claim 2, wherein said nickel-containinglayer has a thickness between 1 and 10 micrometers.
 4. The chip packageof claim 1, wherein said second metal layer comprises titanium.
 5. Thechip package of claim 1, wherein said metal pad comprises copper.
 6. Thechip package of claim 1, wherein said substrate comprises a solder mask,a second contact point in a channel in said solder mask, a third contactpoint in said channel, wherein said second contact point is separatefrom said third contact point, and wherein said channel has a firstsidewall and a second sidewall opposite to and substantially parallelwith said first sidewall, a first interconnect covered by said soldermask and connected to said second contact point through said firstsidewall, and a second interconnect covered by said solder mask andconnected to said third contact point through said second sidewall,wherein said solder is joined with said second contact point.
 7. A chippackage comprising: a substrate; a semiconductor device over saidsubstrate, wherein said semiconductor device comprises a siliconsubstrate, a dielectric layer under said silicon substrate, a firstmetal layer under said dielectric layer, wherein said first metal layercomprises a metal pad and a metal piece separate from said metal pad andneighboring said metal pad, and a polymer layer under said dielectriclayer, under said metal pad, under said metal piece and in a gap betweensaid metal pad and said metal piece, wherein an opening in said polymerlayer is under a first contact point of said metal pad, and said firstcontact point is at a top of said opening; a copper-containing layerbetween said first contact point and said substrate, wherein saidcopper-containing layer is connected to said first contact point throughsaid opening; a second metal layer between said first contact point andsaid copper-containing layer, wherein said second metal layer is on saidfirst contact point, on a bottom surface of said polymer layer and insaid opening, wherein said bottom surface has a first region directlyover said second metal layer and directly under said metal pad and asecond region directly under the middle of said gap, wherein said firstregion is at a substantially same horizontal level as said secondregion, and there is no significant step between said first region andsaid second region, and wherein said copper-containing layer isconnected to said first contact point through said second metal layer; asolder between said copper-containing layer and said substrate, whereinsaid solder is joined with said substrate, and wherein said solder isconnected to said copper-containing layer; and an underfill between saidsemiconductor device and said substrate, wherein said underfill contactswith said semiconductor device and said substrate and encloses saidsolder.
 8. The chip package of claim 7, wherein said second metal layercomprises titanium.
 9. The chip package of claim 7, wherein said metalpad comprises copper.
 10. The chip package of claim 7, wherein saidcopper-containing layer has a thickness between 10 and 100 micrometers.11. The chip package of claim 7, wherein said substrate comprises asolder mask, a second contact point in a channel in said solder mask, athird contact point in said channel, wherein said second contact pointis separate from said third contact point, and wherein said channel hasa first sidewall and a second sidewall opposite to and substantiallyparallel with said first sidewall, a first interconnect covered by saidsolder mask and connected to said second contact point through saidfirst sidewall, and a second interconnect covered by said solder maskand connected to said third contact point through said second sidewall,wherein said solder is joined with said second contact point.
 12. A chippackage comprising: a substrate; a semiconductor device over saidsubstrate, wherein said semiconductor device comprises a siliconsubstrate, a dielectric layer under said silicon substrate, a firstmetal layer under said dielectric layer, wherein said first metal layercomprises a metal pad and a metal piece separate from said metal pad andneighboring said metal pad, and a polymer layer under said dielectriclayer, under said metal pad, under said metal piece and in a gap betweensaid metal pad and said metal piece, wherein an opening in said polymerlayer is under a first contact point of said metal pad, and said firstcontact point is at a top of said opening; a copper-containing layerbetween said first contact point and said substrate, wherein saidcopper-containing layer is connected to said first contact point throughsaid opening; a second metal layer between said first contact point andsaid copper-containing layer, wherein said second metal layer is on saidfirst contact point, on a bottom surface of said polymer layer and insaid opening, wherein said bottom surface has a first region directlyover said second metal layer and directly under said metal pad and asecond region directly under the middle of said gap, wherein said firstregion is at a substantially same horizontal level as said secondregion, and there is no significant step between said first region andsaid second region, and wherein said copper-containing layer isconnected to said first contact point through said second metal layer; asolder between said copper-containing layer and said substrate, whereinsaid solder is joined with said substrate, and wherein said solder isconnected to said copper-containing layer; a nickel-containing layerbetween said copper-containing layer and said solder; and an underfillbetween said semiconductor device and said substrate, wherein saidunderfill contacts with said semiconductor device and said substrate andencloses said solder.
 13. The chip package of claim 12, wherein saidsecond metal layer comprises titanium.
 14. The chip package of claim 12,wherein said metal pad comprises copper.
 15. The chip package of claim12, wherein said copper-containing layer has a thickness between 10 and100 micrometers.
 16. The chip package of claim 12, wherein saidnickel-containing layer has a thickness between 1 and 10 micrometers.17. A chip package comprising: a substrate; a semiconductor device oversaid substrate, wherein said semiconductor device comprises a siliconsubstrate, a dielectric layer under said silicon substrate, a firstmetal layer under said dielectric layer, wherein said first metal layercomprises a metal pad and a metal piece separate from said metal pad andneighboring said metal pad, and a polymer layer under said dielectriclayer, under said metal pad, under said metal piece and in a gap betweensaid metal pad and said metal piece, wherein an opening in said polymerlayer is under a first contact point of said metal pad, and said firstcontact point is at a top of said opening; a nickel-containing layerbetween said first contact point and said substrate, wherein saidnickel-containing layer is connected to said first contact point throughsaid opening; a second metal layer between said first contact point andsaid nickel-containing layer, wherein said second metal layer is on saidfirst contact point, on a bottom surface of said polymer layer and insaid opening, wherein said bottom surface has a first region directlyover said second metal layer and directly under said metal pad and asecond region directly under the middle of said gap, wherein said firstregion is at a substantially same horizontal level as said secondregion, and there is no significant step between said first region andsaid second region, and wherein said nickel-containing layer isconnected to said first contact point through said second metal layer; asolder between said nickel-containing layer and said substrate, whereinsaid solder is joined with said substrate, and wherein said solder isconnected to said nickel-containing layer; and an underfill between saidsemiconductor device and said substrate, wherein said underfill contactswith said semiconductor device and said substrate and encloses saidsolder.
 18. The chip package of claim 17, wherein said second metallayer comprises titanium.
 19. The chip package of claim 17, wherein saidmetal pad comprises copper.
 20. The chip package of claim 17, whereinsaid nickel-containing layer has a thickness between 1 and 10micrometers.